The present invention relates to the testing of integrated circuits. More particularly, the present invention relates to the testing of integrated circuits using an object oriented programming language.
With the high level of complexity of modern integrated circuits (ICs), it is becoming increasingly difficult to test the ICs to ensure that they are manufactured with no defects. Complex ICs are often tested or verified during production to make sure they function properly. Generally, a tester applies electric stimuli to the circuit and measures the circuit""s response to such stimuli to make sure that it is functioning properly. In order to adequately test the various functional blocks in a typical circuit, long test patterns are often designed.
A typical tester uses a test description language (TDL) for testing a circuit. A test description language is a special language used by a tester to drive the circuit being tested with stimuli, in the form of test patterns, and check the response of the device to such stimuli. A series of test patterns is known as a pattern set. Each pattern specifies the logic values of the inputs and outputs of a circuit during one clock cycle. Each pattern in a pattern set is applied sequentially to the circuit.
Boundary scan testing using Boundary Scan Description Language (BSDL), as further described in IEEE 1149.1 and is well known to those of ordinary skill in the art, is commonly utilized to test the interconnections between ICs that comprise a system. The BSDL format file contains the details of every pin of an IC. The ICs can include, for example, application specific integrated circuits (ASICs), hybrids, and circuit boards. For boundary scan test capability, a circuit includes scan circuits that are capable of isolating device input circuits and output circuits from the interior logic of the device and directly accessing such input circuits and output circuits, which allows special interconnection test patterns to be applied and observed without interference from the interior logic functions.
Boundary scan test capability is commonly implemented with boundary scan cells respectively associated with those input circuits and output circuits for which boundary scan testing capability is being provided, with each boundary scan cell containing a scan flip-flop. Boundary scan chip architecture is commonly known to those of ordinary skill in the art and will thus not be discussed. The scan flip-flops are arranged into a register chain that is capable of operation in serial and parallel modes, so that test patterns can be loaded serially, applied in parallel, and test results can be read out serially.
For testing, special interconnection test patterns are serially loaded into scan flip-flops for device output circuits. After a test pattern is loaded, the output scan cells containing the test pattern are switched to drive their associated output circuits in accordance with the test pattern. Subsequently, the signals observed on input circuits are stored in associated input scan flip-flops. The stored inputs are then serially read out to evaluate the test. A further test pattern can be serially loaded into output scan flip-flops while stored inputs are being serially read out.
Boundary scan test patterns are basically designed to drive or toggle each pin of the device to the high state and low state at different times. However, currently, for every device tested, its own dedicated test bench must be developed to achieve the toggling of every pin in the device. Thus, a generic methodology for toggling every pin of a digital device is not available. Accordingly, what is needed is a solution that allows the toggling of every pin of any digital device.
The present invention provides a solution for converting a boundary scan description language (BSDL) file to a hardware verification language (HVL) test program file. The BSDL file is scanned for header information and the header information is stored in a header object. The BSDL file is then scanned for pin information, the pin information corresponding to at least one pin in the BSDL file having a pin location, and stored in a pin object. At least one variable for the HVL test program file is created and bound to one of the pin locations resulting in a binding relationship for each variable. The binding relationships are then stored in a bind object. The present invention is designed to overcome the disadvantages of the prior art.